Currently, there is a drive to implement Seek and Scan Probe (SSP) memory devices for memory applications. SSP devices include a top wafer made from silicon on insulator (SOI) that includes microelectromechanical (MEMS) cantilever beams mounted on a CMOS substrate. A cantilever beam accesses transistor storage devices on a bottom CMOS wafer. To access the storage devices the cantilever beams are constructed to move along the X-Y axis of the lower wafer.
A problem exists with SSP memory devices in that the process of manufacturing the top wafer is expensive. This is because MEMS and CMOS are processed on the wafer. Such a process exhibits low process yields.